The present invention relates to data processing and, more particularly, to logic designs for data processing functions. A major objective of the present invention is to provide an improved binary-counter-based timing generator.
Much of modem progress is associated with the increasing miniaturization of integrated circuits made possible by advances in semiconductor processing technology. Despite the increasing functional density made possible by such advances, there is still a need to implement functions more efficiently and effectively.
One such function of interest is a timing generator used, for example, in a UART ("universal asynchronous receiver/transmitter") communication port. Such a timing generator can include a binary counter for counting clock transitions or other events, memory for storing a maximum count, and match logic for indicating when the binary count reaches the stored maximum count. Typically, a match indication results in an output pulse and a counter reset. The counter can then recount to the maximum count for an iterated pulse generation and counter reset. As a result, pulses are generated periodically.
Depending on the application, the maximum count can be fixed, static programmable, or dynamic (programmable or otherwise). A fixed maximum count can be implemented where there is no need to change the timing period or where the timing period can be adjusted by adjusting the rate of the clock or events being counted. A static programmable maximum count applies where a communications rate is determined after a negotiation between communications devices, e.g., modems, and remains constant once set. A dynamic maximum count applies in applications where a communications rate is regulated to match changing line conditions. The most sophisticated communications systems provide for a dynamic maximum count to continually optimize the communications rate during changing conditions.
Where the maximum count is fixed, it can be hardwired into the match logic. For example, the match logic can include an AND gate with one input for every bit position of the maximum count (expressed in binary notation). For maximum-count bit positions having a 0, the AND input is inverted; for maximum-count bit positions having a 1, the AND input is not inverted. The inverted and uninverted inputs are coupled to respective bit position outputs of the counter. If the counter provides complementary outputs for each bit position, the inverters can be dispensed with and the AND-gate inputs corresponding to maximum-count 0s can be tied to the negative output for the corresponding bit positions.
Where the maximum count is static and programmable, the maximum count is stored in rewrittable memory and the match logic provides for any valid maximum count. A typical approach is to use XNOR gates at each bit position to yield a positive indication whenever the present count and maximum counts at that bit position match. An AND gate then indicates when all the XNOR gates indicate a match. Alternatively, XOR logic can be used instead of the XNOR logic.
This same match logic can be applied to dynamic maximum counts; however, there are cases where the results are not optimal. For example, if, when an eight-bit counter counts reaches 20, the maximum count is changed from 21 to 19, the counter counts to 255, recycles to 0, and counts up to 19 before the next timing pulse was generated. This would result in one period that was an order of magnitude larger than desired, and would delay the onset of the desired periodicity. In practice, the delay can be much larger. Counters as wide as 128 bits are sometimes used to provide a full range of baud rates for a communications systems; for such counters, the "skip" period can be multiple orders of magnitude larger than desired. One option is to reset the counter every time the maximum count is changed. This would avoid the specific problem mentioned above, but in many more cases would extend the timing period undesirably. For example, if when an eight-bit counter reaches 20, the maximum count is changed from 21 to 22, the period would be almost twice the desired period. In cases where the maximum count changes frequently, the maximum count might never be reached. Of course, there are ways to address each of these problems, but their cost in terms of additional circuit complexity must be considered. What is needed generally is a system for indicating matches between present counts and maximum counts that avoids unduly lengthy timing periods when the maximum count is changed. Preferably, such a system would use less complex rather than more complex match logic.